Recently, progress of semiconductor technology causes improvement of device integration so that a system LSI disposed on one chip has been enlarged. When a trouble on an architecture level is found after being formed such the system LSI on the chip, a lot of time and cost is generated for correcting the system LSI.
Therefore in such a system LSI development, improvement of design quality and development efficiency is carried out as mentioned below. First, a block or a module of the verified design is reused. Secondly, the system level is verified step by step by using a top-down design method. In the verification of the system level, total system verification technique is necessary. However, circuit scale of the objective system demand high-speed simulation technology, as increasing with a simulation time by simulator verification.
A hardware emulator, for example, a simulation accelerator or the like is used in high-speed simulation technology. The hardware emulator performs simulation by using a cycle base simulator treating the simulator as cycle accuracy or the like, or a programmable device, for example, a FPGA (Field Programmable Gate Array).
The hardware emulator is operated with several digits of higher speed as comparing with the speed of a software simulator, however, the hardware emulator is restricted to emulate in a circuit scale from the view point of the cost or the number of the programmable device. Therefore, a hardware-software co-simulator having a capability of being simulated by harmonizing between the hardware emulator and the software simulator is proposed in Japanese patent Publication (Kokai) No. 2005-332162.
In processing steps to simulate by harmonizing the hardware emulator and the software simulator, generally, a communication speed between the hardware emulator and the software simulator is later than the simulator speeds of the hardware emulator and the software simulator, respectively. Consequently, the communication speed becomes a bottle-neck so that a problem, which means the simulator speed is lowered, is generated.
Then, technique is known that the simulator speed is improved by decreasing communication amount as an approach. In the decrease of communication amount, the software simulator includes only the changed signals in output signals from the hardware emulator to the software simulator.
On the other hand, the method disclosed in Japanese patent Publication (Kokai) No. 2005-332162 has synchronous between the hardware emulator and the software simulator. Because the software simulator decreases communication amount of the co-simulation by incorporate only varied signals so as to make the co-operation speed high.
As a result, synchronous signals are served from the software simulator to the hardware emulator at every cycle. The result provides generation of communication by the synchronous signals at every cycle so as to decrease the co-simulation speed.